The SKY53510/80/40 series from Skyworks enables the distribution of clocks to devices like SerDes for high-speed serial links.
Skyworks has introduced the SKY53510/80/40 family of Low-Power DC to 3.1 GHz Ultra-Low Additive Jitter Differential Clock Buffers. These devices are designed to assist engineers in creating clocking networks for high-speed buses used in PCIe Gen 7 5G/6G, AI, and cloud-based network equipment, setting a new standard in ultra-low jitter clock buffers.
At 156.25 MHz LVPECL, the ultra-low additive jitter ranges from 35 fs RMS typical to -47 fs RMS max, simplifying design and improving signal integrity.
The SKY53510/80/40 family includes a 3:1 input multiplexer (with crystal input), one single-ended output, and up to ten differential outputs, all housed in compact thermally enhanced QFN packages (7×7 mm, 6×6 mm, 5×5 mm). These devices are pin-compatible with industry-standard layouts.
Key applications for these clock buffers include:
- PCIe Gen 3 through Gen 7
- 56G/112G/224G SerDes
- 5G/6G mMIMO radio systems
- SyncE and broadcast video
- Medical imaging
- Aerospace/defense
Additional features of the SKY53510/80/40 series include:
- Universal format translation for various inputs and outputs
- Low power operation with separate core/output voltage supplies
- Integrated LDOs for improved PSRR in noisy environments
- Wide temperature range and low noise floor for reliable performance
Skyworks confirms that these clock buffers are now available for sampling and production orders, along with the SKY53510-EVB development kit.
Filed Under: Featured, Timing
