Click image to enlarge
In the realm of communications buses like PCIe, the distribution of clocks to various circuits across a board is crucial. Clock signals often require level translation while maintaining acceptable levels of jitter. This solution offers multiple output options.
Three devices in this series cover a range from DC to 250 MHz with ultra-low additive jitter (50 fs RMS). These clock fanout buffers are equipped with dual any-format inputs, including options such as LVDS, 800 mV LVDS, LVPECL, CML, LVCMOS, SSTL, HCSL, and HSTL levels that can be selected through an I²C interface.
The series features:
- SKY53511 providing 10 or 20 LVCMOS outputs.
- SKY53581 offering 8 or 16 LVCMOS outputs.
- SKY53541 delivering 4 or 8 LVCMOS outputs.
SKY53512 (10 outputs), SKY53582 (8 outputs), and SKY53542 (4 outputs) represent low-power, DC to 800 MHz clock fanout buffers with ultra-low additive jitter (37 fs RMS 12 kHz-20 MHz). These devices feature dual any-format inputs, 10 HCSL outputs, an I²C interface for programming, operation in a dual 1:n configuration, individual output enable, and compliance with PCIe Gen1/2/3/4/5/6/7 standards (3 fs RMS PCIe Gen7).
The SKY53513 (10 differential outputs or 20 LVCMOS outputs), SKY53583 (8 differential outputs or 16 LVCMOS outputs), and SKY53543 (4 differential outputs or 8 LVCMOS outputs) cover a range from DC to 3.1 GHz with additive jitter of 35 fs RMS 12 kHz-20 MHz. These clock fanout buffers feature dual any-format inputs, an I²C interface for programming, operation in a dual 1:n configuration, individual output enables, and compliance with PCIe Gen1/2/3/4/5/6/7 standards (3 fs RMS PCIe Gen7).
Filed Under: Active Components, ICs, Timing, Timing ICs
